Whatsminer M50S continues to use Samsung’s 8nm chip, today we will talk in detail about what is an ASIC chip.
Bitcoin mining, the process of validating transactions on the Bitcoin network and earning new bitcoins, has transformed into a competitive industry. At the heart of this transformation lies the ASIC chip (Application-Specific Integrated Circuit), a specialized hardware designed exclusively for mining cryptocurrencies. In this blog, we’ll delve into the world of ASIC chips and understand their significance in Bitcoin mining.
Table of Contents
What is An ASIC Chip?
An ASIC (Application-Specific Integrated Circuit) chip is a specialized piece of hardware designed to perform a specific task, typically with superior efficiency and performance compared to general-purpose hardware. Unlike CPUs or GPUs, which are versatile and can perform a wide range of tasks, ASIC chips are purpose-built for a particular application or algorithm.
ASIC chips are commonly used in various fields, including cryptocurrency mining. In the context of mining, ASIC chips are specifically designed to perform the complex calculations required for mining cryptocurrencies, such as Bitcoin or Litecoin, with optimal efficiency. These chips are highly optimized for mining and can provide significantly higher hash rates and energy efficiency compared to traditional CPUs or GPUs.
The advantage of ASIC chips in cryptocurrency mining is their ability to process mining algorithms at a much faster rate and with lower power consumption. By focusing on a specific algorithm, ASICs can achieve remarkable computational power, which is crucial in the competitive mining environment.
However, ASIC chips have limitations. Since they are designed for specific algorithms, they are not adaptable to other tasks or algorithms. If a cryptocurrency changes its mining algorithm or employs ASIC-resistant mechanisms, ASIC miners become obsolete and less effective.
ASICs have played a significant role in the evolution of cryptocurrency mining, driving efficiency and competition within the industry. Their specialized design allows for highly efficient and profitable mining operations for cryptocurrencies that are compatible with ASIC hardware.
ASIC Chip Features
ASIC chips read raw input data signals and immediately produce output signals after internal logic circuit operations, in contrast to conventional chips like CPUs that produce results by reading and carrying out instructions from external program code.
Advantages
Compared with CPU, GPU, FPGA, and other types of chips, As shown in the following areas, ASIC chips have numerous benefits when used in dedicated systems.
① Area benefit: ASIC chips are made to avoid redundant logic, processing, register, storage, and other architectures. They are constructed as pure digital logic circuits, which helps to minimize the chip area. Small area chips can be handled by cutting out more chips from a single wafer of the same size, allowing businesses to save money on wafer costs.
② ASIC chips have an advantage in terms of energy consumption over CPU, GPU, and FPGA because they use less energy per unit of computation. For example, while GPU uses about 0.4 watts of electricity per unit of computation, ASIC uses only about 0.2 watts, making it easier to meet the energy requirements of new smart home appliances.
③ Advantage of integration: Because ASIC chip systems, circuits, and processes are designed specifically for each customer, they are highly integrated, enabling high-performance integrated circuits to be produced.
④ ASIC chips are significantly less expensive than CPU, GPU, and FPGA chips due to their small size, rapid operation, and low power consumption. ASIC chips currently cost an average of $3 on the international market. In the long run, it is anticipated that the cost of ASIC chips will continue to drop once mass production is achieved.
Disadvantages
① ASIC chips require physical design and reliability verification for the finished products, have lengthy design and development cycles, and are highly customized.
② Algorithms are extremely important to ASIC chips. ASIC chips have a high update frequency because artificial intelligence algorithms are updated and iterated at a rapid pace.
③ ASIC finished products are at increased risk of being discontinued from the market due to the high level of customization found in ASIC chips and the lengthy R&D cycle.
Classification of ASIC Chips
ASIC chips Classification
(1) According to the Degree of Customization
ASIC chips can be divided into three categories: programmable ASIC chips, semi-custom ASIC chips, and full-custom ASIC chips.
① Full-custom ASIC Chips
One of the most customized chips are full-custom ASICs, in which engineers design logic units for various functions based on various circuit structures and construct analog circuits, memory cells, and mechanical structures on the chipboard. Mask boards, which also connect the ASIC chip’s mask boards to the logic cells, are highly customized.
With an average design time of more than 9 weeks per chip module, fully customized ASIC chips are expensive to create. For advanced applications, this kind of chip is frequently used.
Full-custom ASIC chips are more efficient and consume less power than semi-custom ASIC chips. A full-custom ASIC chip’s average arithmetic output is roughly 8 times higher for the same function than a semi-custom ASIC chip’s average arithmetic output under the same process, and a full-custom ASIC chip with a 24nm process performs better than a semi-custom ASIC chip with a 5nm process.
② Semi-custom ASIC Chips
The majority of the logic cells used in semi-custom ASICs are drawn from the standard logic cell library, but some of them are specially created to meet particular needs. Compared to a fully customized ASIC chip, there is a lower design cost and more flexibility.
Semi-custom ASICs can be divided into gate array chips and standard cell chips based on the number of standard logic cells and custom logic cells.
a. Gate Array ASIC Chip
Structured, channelless, and channeled gate arrays are all types of gate array ASIC chips. Gate array ASIC chip structure on the silicon wafer predetermined transistor position can not be changed, the designer mostly through the change of the chip bottom metal layer and other ways to adjust the logic unit interconnection structure.
Channeled gate array ASIC chips: the transistor positions of these chips are highly fixed, and designers can lay out the circuits in the predefined blank space between the transistor rows.
Channeled gate array ASIC chip
Channelless gate array ASIC chips: Designers typically wire above the gate array cells in a channelless structure because there is no space for circuit layout between transistor rows.
Channelless gate array ASIC chip
Structured gate array ASIC chip: A basic gate array row and an embedding block make up this structure. Although it limits the size of the chip, the embedding block increases the flexibility of the circuit layout. With this design, the design cost is lower, the turnaround time is reduced, and the line layout area is utilized more effectively.
Structured gate array ASIC chip
b. Standard Cell ASIC chip
These logic cells were chosen from a library of standard cells to make up this type of ASIC chip. The standard cells can be organized by designers to suit their algorithm’s needs. The standard cell ASIC chip architecture also allows for the use of fixed blocks, such as microcontrollers and processors, in addition to standard cells.
Standard Cell ASIC Chip
③ Programmable ASIC Chip
FPGA chips and PLD chips are two subcategories of programmable ASIC processors. This report only takes PLD (Programmable Logic Device) into account as a subcategory of programmable ASIC chips because an increasing number of research institutions and companies categorize FPGA chips as different from ASIC chips in actual production.
PLDs, or programmable logic devices, contain a matrix of basic logic cells, flip-flops, latches, etc. in their structure, and their interconnected parts exist as individual modules. PLDs can be programmed by designers to satisfy some requirements for special applications.
(2) According to the Terminal Function
Depending on the terminal function, ASIC chips can be categorized as TPU, BPU, or NPU chips.
① Tensor processors called TPUs are exclusively used for machine learning. For instance, Google created a programmable AI accelerator for the Tensorflow platform in May 2016. This accelerator has an internal instruction set that activates whenever the Tensorflow program updates or changes its algorithms.
② The Horizon Technology-proposed embedded AI processor architecture is known as BPU, or Brain Processor Unit.
③ NPU is a neural network processor that directly processes massive amounts of electronic neuron and synapse data using a deep learning instruction set while simulating human synapses and neurons at the circuit layer.
Jack Dorsey’s nano Bitcoin mining chip heads to prototype
Block has completed the design of its new prototype ASIC chip that it says will fast-track its plan to bring an “open source” Bitcoin mining rig design to market.
Block, the financial services and technology company owned by former Twitter CEO Jack Dorsey, has announced it has completed the prototype design of its new five-nanometre (5nm) Bitcoin mining chip — which it claims is key to decentralizing the supply of Bitcoin mining rigs.
According to a blog post published on April 28, Block explained that developing Bitcoin mining ASIC rigs is both financially and technically challenging. The result of this has been “the excessive concentration of custom bitcoin mining silicon” in the hands of a select few companies. Block deems this centralization harmful to both miners and the Bitcoin network as a whole.
Notably, the San Francisco headquartered company wrote that it plans to make Bitcoin mining technology “open source” where possible by selling standalone ASICs and other hardware components to “optimize innovation and maximize the size of the Bitcoin mining hardware ecosystem.”
The post adds that the steps taken over the past few months will allow the firm to experiment with new designs and aid them in bringing more efficient and affordable Bitcoin mining chips to market. In order to fast-track this development push, Block added that it has purchased a large batch of ASIC chips from Intel.
On April 18, Intel announced that it would halt taking new orders for its Blockscale 1000 Series ASICs by Oct. 20 and end shipping in April 2024 as part of cost-cutting measures. Block says this large intake of ASICs from Intel will help accelerate the development of its proprietary 3nm chip, which it claims upon its release, would be the most advanced chip to date.
“We can now focus our design team exclusively on cutting edge three nanometer ASIC development.”
The scale of a nanometer (1nm) is approximately equivalent to the width of two silicon atoms. As parts of the chips become smaller, it allows for more transistors to fit into a silicon die of the same size. By reducing the overall size, the electric current travels less distance in the circuit to perform a calculation, which means that overall efficiency is improved and the amount of heat produced is decreased.
It’s worth noting that 5 nanometre ASIC chips have been around for some time, with the earliest 5nm ASIC being released in 2021 from Chinese mining firm Canaan. Currently, most Bitcoin mining ASICs run on 5nm chips; however, no company has made their ASIC chip designs open source.
Conclusion
ASIC chips have revolutionized Bitcoin mining, propelling the industry into a new era of efficiency and competitiveness. By harnessing the power of these specialized hardware solutions, miners can achieve remarkable hash rates and optimize their profitability. However, it’s essential to navigate the ever-evolving ASIC landscape, considering factors such as cost, ROI, and technological advancements. As the industry continues to evolve, staying informed and adapting to changing conditions will be key to mining success in the Bitcoin ecosystem.
